| PART |
Description |
Maker |
| 74LCX112SJ 74LCX112 74LCX112M 74LCX112MTC 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
Fairchild Semiconductor, Corp.
http://
FAIRCHILD[Fairchild Semiconductor]
|
| MAX685 MAX685EEE |
Dual-Output Positive and Negative / DC-DC Converter for CCD and LCD
Dual D-type Positive-Edge-Triggered Flip-Flops With Preset And Clear 14-CFP -55 to 125
Dual-Output Positive and Negative, DC-DC Converter for CCD and LCD
|
Maxim Integrated Products, Inc.
MAXIM[Maxim Integrated Products]
|
| SN74LS107D SN74LS107N SN54LS107J SN54LS107A |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
Motorola Inc
MOTOROLA[Motorola Inc]
|
| SN54LS112A SN54LS112J 74LS112 SN74LS112N SN74LS112 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
MOTOROLA[Motorola Inc]
|
| DV74AC112 |
Dual JK Negative edge-triggered flip-flop
|
AVG Semiconductors(HITEK)
|
| 74HC73 74HC73D 74HC73DB 74HC73N 74HC73PW 74HCT73 |
Dual JK flip-flop with reset; negative-edge trigger
|
PHILIPS[Philips Semiconductors]
|
| 74HC107D-Q100 74HCT107D-Q100 74HC107PW-Q100 |
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors
|
| IDT74LVC112A 74LVC112A_DS_87847 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
From old datasheet system
|
IDT
|
| 74F114PC |
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
|
Fairchild Semiconductor
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| CD74HCT107E CD74HC107M96 CD74HC107MT |
<font color=red>[Old version datasheet]</font> Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
TI store
|
